1. Field of the Invention
The present invention relates to a level shift circuit in a power element drive integrated circuit.
2. Description of the Prior Art
As power element drive integrated circuits for home electric appliances and industries, in place of conventional photocouplers, high-voltage integrated circuits (HVIC) have been popularly used. Depending on applications, a voltage of several 100 V which is close to a power supply voltage of a power element is applied to the HVIC itself. For this reason, a high-withstand-voltage circuit is indispensable. Therefore, the circuit is manufactured by high-voltage processes for semiconductors.
In many cases, this HVIC is directly driven by a signal from a microcomputer. For this reason, in order to transmit a low-potential signal (about 5 V) of a microcomputer, a level shift circuit for converting the signal into a signal having a high potential (several 10 V) is constituted. As the level shift circuit, a high-withstand-voltage signal transmission element is used, and has a withstand voltage higher than the power supply voltage of the power element.
As this high-withstand-voltage element, a MOS transistor is mainly used. However, in an operation state in which a voltage of several 100 V is applied, when an overcurrent flows in the high-withstand-voltage MOS transistor, the element may be overheated to be broken.
This point will be described below by using a conventional HVIC level shift circuit shown in FIG. 6. This circuit is constituted by an HVIC power supply VCC (1), a power element power supply HV (2), an offset power supply VS (3) using an output voltage as a power supply, a floating power supply VB (4) having a negative electrode connected to the offset power supply VS (3), a high-withstand-voltage MOS transistor (5), a drive inverter (7) for the high-withstand-voltage MOS transistor (5), a resistor (9) for pulling up the drain of the high-withstand-voltage MOS transistor (5) to the voltage of the floating power supply VB (4), and a diode (10) inserted between the drain of the high-withstand-voltage MOS transistor (5) and the VS (3).
When a P-ch MOS transistor of the drive inverter (7) is turned on by an input signal to pull up the gate voltage of the high-withstand-voltage MOS transistor (5), the high-withstand-voltage MOS transistor (5) is turned on. A drain current at this time is supplied from the floating power supply VB (4) through the resistor (9). When this drain current is sufficient, a drain potential Vds of the high-withstand-voltage MOS transistor (5) exceeds the threshold value of the inverter (power element) connected to the output of the high-withstand-voltage MOS transistor (5), and a drive signal is sent to the gate of the power element.
When the offset power supply VS (3) is boosted to several 100 V, the diode (10) inserted between the offset power supply VS (3) and the drain of the high-withstand-voltage MOS transistor (5), and the drain potential Vds is clamped to VS-VF (forward voltage of the diode (10)). When the current sink capability of the high-withstand-voltage MOS transistor (5) is sufficient, a drain current is supplied from the offset power supply VS (3) through the diode (10).
The current sink capability of the high-withstand-voltage MOS transistor (5) increases depending on a voltage Vgs applied across the gate and the source. For this reason, in a state in which a voltage of several 100 V is applied across the drain and the source, when a voltage (15 to 20 V) which is close to the power supply Vcc is applied across the gate and the source, an overcurrent flows in the high-withstand-voltage MOS transistor (5), and element breakdown may occur.
Since the capacitance (gate capacitance) between the gate and the source of the high-withstand-voltage MOS transistor (5) is considerably large, when a very short input signal having a time which is taken to cause the voltage of the high-withstand-voltage MOS transistor (5) to reach the gate voltage at which the high-withstand-voltage MOS transistor (5) operates is input, the high-withstand-voltage MOS transistor (5) is not turned on. As a result, a response speed is low.